Lesson Notes
Grade 12
First Term
Second Term
Third Term
Grade 13
Second Term
Grade
13
Lesson Overview
Unit 9 introduces semiconductors, diodes, rectification, Zener regulation, transistors, FETs, operational amplifiers, and digital logic (logic gates and flip-flops). This unit is essential for understanding modern electronic devices and circuits.
1. Core Concepts (Short Notes)
9.1 Semiconductors & Diodes
Intrinsic semiconductor: pure Si/Ge.
Extrinsic semiconductor: doped (p-type or n-type).
p–n junction forms depletion region & potential barrier (~0.7 V for Si).
Diode characteristics: forward & reverse bias.
Diode symbol: triangle and bar.
9.2 Rectification
Half-wave: uses one diode.
Full-wave bridge: uses four diodes.
Smoothing: capacitor filters ripples.
9.3 Zener Diode
Operates in reverse breakdown region.
Used for voltage regulation.
9.4 Transistors (BJT)
npn / pnp bipolar devices.
Three regions: base (thin), emitter (heavily doped), collector.
Common emitter configuration most common.
Transistor regions:
Cut-off
Active (amplification)
Saturation
9.5 Amplifiers
Current amplification: I_C = βI_B.
Voltage amplification: output is 180° out of phase.
9.6 FET (Field Effect Transistor)
JFET: n-channel and p-channel.
Voltage-controlled device.
9.7 Operational Amplifiers (Op-Amps)
High-gain differential amplifier.
Golden Rules:
Input currents ≈ 0.
V⁺ = V⁻ (for linear region).
Inverting & non-inverting configurations.
Voltage comparator.
9.8 Logic Gates
Basic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR.
Truth tables & Boolean expressions.
SR Flip-flop for memory.
2. Detailed Notes for Each Section
9.1 Intrinsic & Extrinsic Semiconductors
Intrinsic
Pure Si/Ge.
Temperature increases → electron-hole pairs increase.
Extrinsic
p-type: doped with Group III (acceptors → holes).
n-type: doped with Group V (donors → electrons).
p–n Junction
Formation of depletion region.
Potential barrier prevents further diffusion.
Typical values:
Si: 0.7 V
Ge: 0.3 V
9.2 Diode Characteristics
Forward Bias
Reduces barrier → allows current.
Current rises sharply after knee voltage.
Reverse Bias
Depletion widens → small leakage current.
Breakdown occurs if reverse voltage > PIV.
I-V Characteristics
Non-linear.
Important points: knee voltage, reverse breakdown.
9.3 Rectification
Half-Wave Rectifier
Only positive half allowed.
Low efficiency.
Full-Wave Bridge
Four diodes.
Uses both halves of AC.
Smoothing
A capacitor reduces ripple.
Ripple decreases with larger capacitance.
9.4 Zener Diode Regulation
Operates in reverse breakdown.
Maintains constant output voltage.
Requires series resistor for safety.
9.5 Bipolar Junction Transistor (BJT)
Modes of Operation
Cutoff: I_B ≈ 0; no conduction.
Active: I_C ≈ βI_B; amplifier region.
Saturation: Both junctions forward biased.
Common-Emitter Amplifier
Input: base.
Output: collector.
Voltage gain: inverted (180° phase shift).
Characteristics
Input: I_B vs V_BE.
Output: I_C vs V_CE.
Transfer: I_C vs I_B.
9.6 JFET (Junction Field Effect Transistor)
Features
Unipolar (single carrier type).
Gate reverse-biased.
Drain current controlled by gate voltage.
Common-Source Configuration
Voltage gain without phase inversion (for some cases).
Characteristic curves: I_D vs V_DS.
9.7 Operational Amplifiers
Symbol & Pins
non-inverting input
– inverting input
Output terminal
Power supply pins
Golden Rules
Input currents ≈ 0.
V⁺ = V⁻ in linear mode.
Inverting Amplifier
Gain:
A_v = – R_f / R_in
Non-Inverting Amplifier
Gain:
A_v = 1 + (R_f / R_in)
Comparator
Output saturates to ±V_supply.
9.8 Logic Gates & Boolean Algebra
Basic Gates
AND, OR, NOT.
Universal gates: NAND, NOR.
XOR & XNOR.
Truth Tables
Used to predict output states.
SR Flip-Flop
Basic memory element.
Based on NOR or NAND gates.
Stores 1 bit.
Timing Diagrams
Show how outputs follow inputs over time.
3. Formula Summary (Unit 9)
Current gain: β = I_C / I_B
Inverting Op-Amp gain: A_v = – R_f/R_in
Non-inverting gain: A_v = 1 + R_f/R_in
Rectifier efficiency: η ≈ 40% (half-wave), 80% (full-wave)
4. Common Mistakes to Avoid
Confusing p-type with positive charge carriers (they are holes, not protons!).
Not including series resistor with Zener diode.
Using transistor without biasing.
Forgetting phase inversion in CE amplifiers.
Mixing XOR and OR logic conditions.
5. Exam Tips
Draw semiconductor diagrams clearly (show depletion region!).
Label diode I-V curves properly.
Show transistor regions (cutoff, active, saturation) on graphs.
Use truth tables to design logic circuits.
For op-amp questions, always apply Golden Rules.
6. Quick Revision Table
Topic | Key Points |
Diodes | p–n junction, rectifier, Zener |
Transistors | Amplification, β, CE mode |
FET | Voltage-controlled |
Op-Amps | Golden rules, amplifiers |
Logic Gates | AND, OR, NOT, NAND, NOR, XOR |
Flip-Flops | SR latch memory |
වියාචනය (Disclaimer)
Idasara Academy ඉගෙනුම් සම්පත් නිර්මාණය කර ඇත්තේ සිසුන්ට මගපෙන්වීම, පුහුණුව සහ අධ්යයන උපායමාර්ග ලබාදී සහයෝගය දැක්වීමටය.
කෙසේ වෙතත්, සියලුම විභාග සහ නිල අවශ්යතා සඳහා, සිසුන් අනිවාර්යයෙන්ම ශ්රී ලංකා අධ්යාපන අමාත්යාංශයේ, අධ්යාපන ප්රකාශන දෙපාර්තමේන්තුව විසින් ප්රකාශයට පත් කරන ලද නිල පෙළපොත් සහ සම්පත් පරිශීලනය කළ යුතුය.
ජාතික විභාග සඳහා අන්තර්ගතයේ නිල බලය ලත් මූලාශ්රය වනුයේ රජය විසින් නිකුත් කරනු ලබන මෙම ප්රකාශනයි.
